`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/09/11 10:03:41
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "sys_parameter.vh"

module top
(   
input  sys_clk,
output uart_txd
);


wire   clk_out1;
wire   locked;


clk_wiz_0 clk_wiz_0
(
 .clk_out1(clk_out1),
 .locked(locked),       
 .clk_in1(sys_clk)
);     


uart_top #(
    .UART_CLK_PARAM ( 32'd100_000_000 ),          
    .UART_BPS_TX    ( 32'd115_200     ))     
 u_uart_top (
    .sys_clk                 ( clk_out1    ),
    .sys_rst_n               ( locked      ),

    .uart_txd                ( uart_txd    ) 
);



endmodule
